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Abstract:
More and more analog and mixed-signal (AMS) blocks are integrated into system on chip (SoC) platform due to intense market competition. In this paper, we present a 16 bit successive approximation register (SAR) analog-to-digital converter (ADC) IP that is much smaller and less power cost than other recently reported SAR ADCs. In addition, we use several techniques to improve area and power. This work has multi input channels with programing input scale. A high accuracy reference voltage and low noise comparator proposed in this design. We also design on-chip calibration and oversampling digital filter to achieve a higher SNR.
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PROCEEDINGS OF 2018 IEEE 3RD ADVANCED INFORMATION TECHNOLOGY, ELECTRONIC AND AUTOMATION CONTROL CONFERENCE (IAEAC 2018)
Year: 2018
Page: 998-1002
Language: English
Cited Count:
WoS CC Cited Count: 1
SCOPUS Cited Count:
ESI Highly Cited Papers on the List: 0 Unfold All
WanFang Cited Count:
Chinese Cited Count:
30 Days PV: 7
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