Translated Abstract
Cardiac pacemaker is a medical device implanted in the human body, which can sense the ECG signal of the body through electrodes and generate electrical impulses delivered by electrodes to contract the heart muscles and regulate the electrical conduction system of the heart. Cardiac pacemaker is often composed of a MCU, an application specific integrated circuit (ASIC) implementing the functions of sensing and pacing, a telemetry circuit and necessary discrete components. For the pacemaker powered by a battery, how to improve the performance of the ASIC and reduce the power and area of the ASIC as far as possible are the emphasis and difficulties in circuits design. To meet the requirements of low power, low noise, small area and multifunctions for pacemakers, in this dissertation the sensing amplifier and bandgap referenc are studied and improved firstly and on this basis a low power and multifunctional ASIC is proposed.
Firstly, for improving the integration level and reducing power and noise, a low-power and low-noise capacitive-feedback amplifier with a current-reused OTA is proposed. To improve the noise-power efficiency, the proposed OTA employs a current-reused architecture, which adopts an inverter-based differential input stage for low noise, and a class-AB output stage for large output range and high gm/I efficiency. The driving branch of the class-AB output stage is merged into the input stage to realize current reuse and reduce power consumption further. Fabricated in DongBu 0.35-μm CMOS process, the amplifier consumes 160 nA from a 2-V supply, while achieving an input-referred noise of 2.05 μVrms, corresponding to a noise efficiency factor (NEF) of 2.26. The measured common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) exceed 65 dB and 70 dB, respectively. The total harmonic distortion (THD) is less than 1% with a 15-mVpp input at 20 Hz. In addition, the human heart signal test proves the proposed amplifier meets the requirement of sensing circuit in pacemakers.
Secondly, for overcoming the disadvantages of the large resistor value and large chip area in resistive voltage reference under low power consumption, a resistor-less low-power voltage reference circuit based on high-slope proportional-to-absolute-temperature (PTAT) voltage generator is proposed. For enhancing the temperature coefficient of PTAT voltage, a new topology that combines two mechanisms to generate PTAT voltage is proposed. Hence, the number of the required PTAT voltage generators is reduced and low power consumption is achieved. The proposed voltage reference is fabricate in HHNEC 0.35-μm CMOS process and occupies an area of 0.019mm2. Measurement results show that the voltage reference achieves a 1.098-V reference voltage with a temperature coefficient of 31.3 ppm/℃, while consuming only 40 nA under a 3.3 V power supply.
Thirdly, for increasing the efficiency of the pulse generator and realizing the pulse amplitude adjusted on demand, a programmable high-voltage pulse generator based on ultra-low-frequency charge pump is proposed. In the proposed pulse generator, the output load of the charge pump is just the prasitic capacitor of the switches. Thus, the charge pump can be driven by a low-frequency clock and then can lower the dynamic power and achieve high efficiency. For enhancing the efficiency further, two improved charge pumps are proposed to eliminate the body effect and leakage current. In addition, The proposed pulse generator provides current in opposite direction in the charging and pacing phases which ensures ion balance in the heart. Measurement results show that the proposed pulse generator can provide fully programmable stimulating pulse with high efficiency.
Finally, a low-power, multifunctional mixed-signal ASIC is proposed for triple-chamber pacemakers. Besides the above proposed techniques, the following techqiques are also proposed. According to the characteristics of the heart electrical conduction, a low-power control strategy is proposed in the sensing channel, in which the sensing circuit is turned on by a sensing command and turned off automatically by a valid sensing event to reduce the average power consumption. Resistance measurement function based on bidirectional current injection is also integrated in the ASIC to reflect the connection status and pathological status of the patient’s heart. The ASIC is fabricated in HHNEC 0.35-μm Bipolar-CMOS-DMOS (BCD) process with a chip area of 3.8 mm×3.8 mm. Measurement results show that the ASIC can sensing ECG signal properly and the magnitude of the stimulus pulse can be programmed from 0.1 to 7.5 V with 0.1-V step. Almost linear heart resistance measuring is achieved in the resistance range of 250 to 4000 Ω. The average current consumption is 4 μA under typical pacing algorithms from a 2.8-V power supply. The ASIC has been applied in a real pacemaker device and proved by the animal experiment.
Translated Keyword
[Application specific integrated circuit, Bandgap reference, Implantable cardiac pacemaker, Low power, Sensing amplifier]
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