Translated Abstract
With the rapid development of high-performance computing, 3D image processing, digital signal processing and other application scenarios, higher requirements are asked for the processing capabilities of floating point units. According to statistics, in all floating point operations, the use frequencies of floating point addition, floating point subtraction, and floating point multiplication are 25%, 15%, and 37%, respectively. Floating point addition and floating point subtraction share floating point adders. Therefore, the design of floating point arithmetic unit is focused on the design of floating point adder and floating point multiplier.
Based on the most widely used IEEE 754 single precision floating point number standard, the existing floating point addition algorithm and floating point multiplication algorithm are studied in this thesis, then the research and design of single precision high performance floating point addition unit and floating point multiplication unit are completed. Specifically, the content of this thesis has the following points. Firstly, the IEEE 754 single precision floating point number system is analyzed, including floating point representations, floating point exceptions and rounding modes. Secondly, the One-Path method, Two-Path method and Three-Path method in floating point addition are analyzed. Based on the Three-Path method, the structure of combined rounding is adopted. The leading zero anticipation module and exception detection module are designed. Besides, the logic of the parallel prefix Ling adder is improved. Floating point addition unit is designed based on the above improvements. Thirdly, floating point multiplication algorithm is analyzed. Binary multiplier is designed, including adopting modified Booth2 encoding method and modified partial product arrays to generate partial products. Partial products are compressed by using 3:2 compressor, 4:2 compressor, 5:2 compressor and Wallace tree. Floating point multiplication unit is designed based on above improvements. Fourthly, the basic concepts and methods of verification and synthesis are introduced.the verification and synthesis of floating point addition unit and floating point multiplication unit are performed. The verification results show that the logical function of floating point addition unit and floating point multiplication unit is correct. The synthesis results show that the performance of the design in this thesis is improved a lot compared to Xilinx floating point IP, DesignWare floating point IP and references.
Translated Keyword
[Booth2 algorithm, Floating point addition, Floating point multiplication, Ling adder]
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