Translated Abstract
In recent years, with the continuous improvement of the data transmission rate of the digital system, the traditional parallel interface has been widely replaced by serial interface based on serialize/deserialize (SerDes) technology. SerDes interface uses high-speed differential signal to transmit data, and clock information is hidden in the data by coding, so that the clock pin and the corresponding transmission line can be omitted. As the serial transmission rate is becoming higher and higher, the length of the unit interval is becoming shorter and shorter, the requirements to the jitter performance of the system is getting higher and higher. Phase locked loop (PLL) and clock and data recovery circuit are of vital importance to the SerDes interface: PLL provides high-frequency clock for the interface, and clock and data recovery (CDR) circuit extracts clock information from the serial data in the receiver, so as to realize the optimal sampling. Therefore, it is of great academic significance and application value to study the phase locked loop and clock data recovery circuit with high speed and low jitter.
The phase locked loop and clock and data recovery circuit in a 1.6Gbps~2.5Gbps 8B/10B SerDes interface are studied and designed in this thesis. In order to output high quality and low jitter clock in a wide frequency range, a self-biased PLL is used. As a result, damping factor and the ratio of loop bandwidth to reference frequency is decided by the ratio of two capacitances. Therefore, they won’t change with working frequency. The phase domain model of charge pump PLL is built in this thesis. The loop parameters are determined as well. Circuit modules like PFD, charge pump, bias generator and voltage controlled oscillator are designed and simulationed on the circuit level according to the loop parameters of PLL. The layout of PLL is also designed in this thesis. As to CDR, a phase-interpolator-based CDR using digital circuits to control the loop is choosed based on the comparison of the advantages and disadvantages of CDRs of various structures. Through the analysis of the working principle of the system and locking process, each circuit module including high speed sampling circuit, phase detecor, voting circuit, bidirectional shift register, phase selector, phase interpolator and wave shaping circuit is designed and simulationed. A linear phase interpolator based on non-equal current source array is presented to solve the problem of increasing clock jitter arise from the non-linearity of phase interpolator in clock and data recovery circuit. As a result, the output jitter of CDR is reduced significantly.
The overall simulation of the self-biased PLL and phase-interpolator-based CDR is carried out at a supply voltage of 2.5V, SMIC 0.25μm standard CMOS process. The self-biased PLL can output high quality and low jitter clock signal in the frequency range of 800MHz~1.25GHz. The output phase noise is -100dBc/Hz@1MHz. The locking time is 14.3μs and the power consumption is 80mW under 1.25GHz working frequency. The simulation results of the phase-interpolator-based CDR show that the recoverd clock can track the phase of the serial signal and sample at the middle of the unit interval through the loop modulation of the weight control signal. After the linearization method in this thesis is adopted, the jitter of the output clock in the CDR is reduced from 36.72ps to 29.46ps. The power consumption of the entire CDR is 106mW.
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