In　this　paper,　a　new　high-voltage　level　shifter　(HVLS)　structure　is　proposed,　which　has　a　significantly　improved　transient　response　over　existing　structures.　To　overcome　signal　transfer　delay　of　the　conventional　HVLS　caused　by　parasitic　capacitance　due　to　high-voltage　MOSFETs,　this　structure　employs　a　novel　circuit　module　＂inverse　Schmitt　trigger＂　to　drive　the　pull-up　transistors　of　conventional　HVLS.　As　a　result,　the　＂Miller　Plateau＂　caused　by　parasitic　capacitance　can　be　minimized.　Hence,　the　overall　transfer　delay　of　the　structure　is　significantly　reduced.　The　simulation　results　based　on　SPECTRE　and　0.5　m　high-voltage　CMOS　process　show　that　compared　to　other　currently　available　structures　whose　transfer　delays　are　several　nanoseconds　on　average,　the　proposed　structure　is　able　to　provide　a　nanosecond　transfer　delay　without　using　large　boost　capacitors　which　are　impractical　to　be　integrated　or　using　complex　logic　units　which　decrease　reliability　of　circuit.　Also,　the　typical　transfer　delay　of　the　proposed　structure　is　a　constant　1.3　ns,　which　is　irrelevant　to　parasitic　capacitance　and　insensitive　to　transfer　voltage　level.