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Abstract：
A high drive current and low power 4T SOI-SRAM cell with 0.5V supply voltage is proposed. This structure adopts Cross-shaped gate n-MOSFET and ultra thin self-body-bias (SBB) resistor. They share the same gate electrode to form the inverter of SRAM cell. The Cross-shaped gate n-MOSFET increases the drive current. Furthermore, the process of SBB resistor is simple and compatible with SOI-CMOS process. The performance and process of the proposed memory cell are simulated by MEDICI and T-SUPREM4. Results show that the ultra thin SBB resistor has a 4.1 x 10(4) on/off-state current ratio and its on-state current closed to 10uA/um is comparable to the n-MOSFET. At 0.5V supply voltage, the memory cell＇s static noise margin (SNM) is about 296mV and the dynamic power dissipation of write and read operation are about 1.6uW and 1.2uW respectively.
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2009 IEEE INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC 2009)
Year： 2009
Page： 453-456
Language： English
Cited Count：
WoS CC Cited Count： 0
SCOPUS Cited Count：
ESI Highly Cited Papers on the List： 0 Unfold All
WanFang Cited Count：
Chinese Cited Count：
30 Days PV： 4
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